This invention relates generally to high-speed synchronous comparator circuits and, more particularly, to comparators of the type used in analog-to-digital converters (ADCs). There are a number of different types of analog-to-digital converters. Perhaps the two most commonly used types are the flash architecture and the successive approximation architecture. Both architectures include comparators, and will be briefly described by way of background.
The flash, or parallel threshold, architecture uses multiple comparators, one for each quantization level. Thus, for a given input signal, all comparators referenced to threshold levels below the input signal will be actuated and all comparators referenced to threshold levels above the input signal will not be actuated. Thus, the comparators produce a "thermometer" code indicative of the binary value of the input signal, and this is further decoded to provide an equivalent digital output signal.
In the successive approximation type of ADC, the input signal is first compared with the analog equivalent of a half-scale reference value stored in a successive approximation register, to determine the most significant bit of the digital value of the input signal. Successively less significant bits are determined by repeatedly updating the register and making comparisons between the input signal and the analog equivalent of the register contents. Each cycle of operation produces one more bit of significance in the digital output.
In all types of ADC, the comparator plays a critical role. It has to compare a relatively small analog differential input signal and produce a large digital output signal. Thus, it ideally needs high gain. Further, the speed of the ADC ultimately depends on the speed of the comparator or comparators used in it.
The present state of the art of comparator circuits uses a circuit configuration referred to as differential current mode logic (DCML). Typically, such a configuration includes a current-mode logic (CML) transistor pair that is used for acquisition, referred to as the acquisition pair, and another pair of transistors also connected in CML, referred to as the latch pair. During an acquisition phase, the latch pair is totally disabled by the action of a clock signal and the acquisition pair is enabled by the same signal. A differential input signal is applied to the acquisition pair. The latch pair is cross-coupled to provide positive feedback to quickly latch and amplify the acquisition signal. During the latching phase, the acquisition pair is disabled and the latching pair is enabled. This switching of the two amplifier pairs leads to some significant disadvantages.
Two important parameters of comparators are its speed and its resolution. As will be further discussed, the speed of comparators of the prior art, such as DCML comparators, is limited by the time needed to switch from acquisition mode to latching mode. Moreover, the resolution obtainable from DCML comparators is inherently limited.
In any comparator, previous values of the input signal tend to create a hysteresis effect, whereby the latch amplifier tends to select the previous polarity of the input signal. When a DCML comparator switches from the latching phase to the acquisition phase, the previously latched signal remains on a pair of high-impedance nodes of the latching pair. This residual value has to be overcome by the new value of the input signal. This effect degrades comparator resolution.
In the DCML comparator, the acquisition pair and the latch pair are being switched on and off, and this creates voltage steps at the common source node of the pair. These voltage steps are typically coupled capacitively back to the signal inputs, by device internal capacitances (gate-source capacitance in field-effect transistor amplifiers, or base-emitter capacitance in bipolar transistor amplifiers). This can result in comparator errors.
Another significant disadvantage of the DCML comparator is that its speed is inherently limited by the time that it takes to switch off the acquisition pair and switch on the latch pair. After the comparator switches from acquisition mode to latching mode, a certain delay time must elapse before the acquisition pair is fully disabled, to ensure that no input signals can feed through to the latching pair. This "hold" time can be a significant portion of the total latching time. If the hold time is shortened, the latch output can be subject to errors. This problem ultimately limits the overall comparator speed. In the DCML comparator, there is a delay between the time that the acquisition pair turns off and the latching pair turns on. During this delay, the signal at the high-impedance nodes of the latching pair leaks away and reduces the initial latch signal available to the latching pair. Therefore, the latching time to obtain a desired output signal level is increased.
It will be appreciated from the foregoing that there is a significant need for improvement in the field of synchronous comparators for use in such applications as analog-to-digital converters. Specifically, what is needed in a comparator is a combination of high speed of operation and high gain in the latching or regeneration phase of operation. Ideally, a comparator should also not be subject to the disadvantages suffered by DCML comparators of the prior art. The present invention meets all of these requirements.